Maat, Franca (2026) Adapting the FELIX readout system for Timepix4 towards future LHCb VELO applications. Master's Thesis / Essay, Physics.
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Abstract
Future high-rate pixel detectors require readout systems that can handle increasing data rates while maintaining timing, synchronization and data integrity. The Front-End LInk eXchange (FELIX) system, originally developed for ATLAS, provides an FPGA-based readout architecture with high-speed optical links and PCIe transfer to a host server. This thesis investigates whether the FELIX FLX-712 can be adapted to receive Timepix4 data as a proof of principle for possible future LHCb VELO readout systems. The FELIX firmware data path was adapted for Timepix4-like fast-link streams and validated using simulation, internal emulator data and hardware tests with a Timepix4 setup at Nikhef. Internal emulator measurements show that data can be received, formatted and transferred correctly, with the rate scaling linearly with the number of active links. Per endpoint, rates range from about 661.7 MB/s for one link to 5293.6 MB/s for eight links. In hardware tests, twelve Timepix4 fast links were connected and valid block synchronization was obtained on the expected channels. Timepix4 heartbeat packets were acquired with FELIX tools. For two tested heartbeat-period settings, the measured rates agreed with expectations based on 40 MHz timing and followed the expected ratio of 129/65. These results demonstrate that the FELIX FLX-712 can receive and process Timepix4-format fast-link data. Further work should test full sensor data, realistic hit occupancies and higher aggregate bandwidth.
| Item Type: | Thesis (Master's Thesis / Essay) |
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| Supervisor name: | Perrevoort, A. and Pellegrino, A. |
| Degree programme: | Physics |
| Thesis type: | Master's Thesis / Essay |
| Language: | English |
| Date Deposited: | 17 Jul 2026 13:47 |
| Last Modified: | 17 Jul 2026 13:47 |
| URI: | https://fse.studenttheses.ub.rug.nl/id/eprint/37449 |
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